1. Field of the Invention
The present invention relates to an insulated gate type semiconductor device and a method for fabricating the same, more particularly relates to an insulated gate type semiconductor device designed to prevent short-circuits, an increase in parasitic capacitance, and an increase in chip size accompanying the formation of a body contact region in a metal-oxide semiconductor field effect transistor (MOSFET) or other insulated gate type semiconductor (IGFET) using a silicon-on-insulator (SOI) substrate and a method for fabricating the same.
2. Description of the Related Art
As will be explained in detail later using the drawings, in an SOI-MOSFET using a separator, short-circuits between the body contact electrode and source and drain electrodes are prevented by the sidewalls provided at the side faces of the separator. If the sidewalls are low in height, however, in the siliciding step, silicon diffuses in the metal film deposited on the surface of the sidewalls as well and alloys the film, so the silicide at that portion cannot be removed. Therefore, there is the problem of short-circuits between the body contact electrode and source and drain electrodes through the silicide layer.
Further, when arranging the transistors in the form of an array as in the normal state of use, when adjoining separators are different in potential, it is necessary to keep the two separated by exactly a constant distance in order to prevent short-circuits between them. Due to this, there is the problem that the chip area is increased.
Further, the width of a separator is dependent on the overlay accuracy in the photolithography step at the time of formation of the separator, the variance in finishing dimensions in the etching step of the separator, the overlay accuracy of the mask at the time of ion implantation in the step of forming the body contact region, etc. Therefore, the area occupied in one transistor becomes the same order as the gate electrode functioning for forming the channel and the parasitic capacitance increases. As a result, there is the problem that the gate delay becomes greater and the performance of the device deteriorates.